View 100390_127764.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

100390 Low Power Single Supply Hex PECL-to-TTL Translator
September 1990 Revised August 2000
100390 Low Power Single Supply Hex PECL-to-TTL Translator
General Description
The 100390 is a hex translator for converting F100K logic levels to TTL logic levels. Unlike other level translators, the 100390 operates using only one +5V supply. Differential inputs allow each circuit to be used as an inverting, noninverting, or differential receiver. An internal reference generator provides VBB for single-ended operation. The standard FAST 3-STATE outputs are enabled by a common active low TTL compatible OE input. Partitioned VCCs on chip are brought out on separate power pins, allowing the noisy TTL VCC power plane to be isolated from the relatively quiet ECL VCC. The 100390 is ideal for applications limited to a single +5V supply, allowing for easy ECL to TTL Interfacing.
Features
s Operates from a single +5V supply s 3-STATE outputs s 2000V ESD protection s VBB supplied for single-ended operation
Ordering Code:
Order Number 100390SC 100390PC 100390QC 100390QI Package Number M24B N24E V28A V28A Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (-40C to +85C)
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
24-Pin DIP/SOIC 28-Pin PLCC
FAST is a registered trademark of Fairchild Semiconductor.
(c) 2000 Fairchild Semiconductor Corporation
DS010897
www.fairchildsemi.com
100390
Logic Symbol
Pin Descriptions
Pin Names D0-D5 D0-D5 Q0-Q5 OE VBB Description Data Inputs (PECL) Inverting Data Inputs (PECL) Data Outputs (TTL) Output Enable (TTL) Reference Voltage (PECL)
Truth Table
Data Inputs (PECL) Dn X L H L H OPEN L H VBB VBB VBB OPEN
H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance U = Undefined
Control Input (TTL) OE H L L L L L L L L L L L
TTL Outputs Comments Qn Z L H U U U L H H L H L Outputs Disable Differential Operation Differential Operation Invalid Input States Invalid Input States Invalid Input States Single Ended Operation Single Ended Operation Single Ended Operation Single Ended Operation Single Ended Operation Single Ended Operation
Dn X H L L H OPEN VBB VBB L H OPEN VBB
Logic Diagram
Detail
www.fairchildsemi.com
2
100390
Absolute Maximum Ratings(Note 1)
Storage Temperature Maximum Junction Temperature VCC Pin Potential to Ground Pin TTL Input Voltage (Note 2) TTL Input Current (Note 2) VBB Output Current ECL Input Potential VCC Differential ECL VCC to TTL VCC Voltage Applied to Output in High State (with VCC = 0V) 3-STATE Output Current Applied to Output in Low State (Max) ESD Last Passing Voltage (Min) Twice the Rated IOL (mA) 2000V
-65C to +150C +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA -5.0 mA to +1.0 mA
GND to ECL VCC + 0.5V
Recommended Operating Conditions
Case Temperature Supply Voltage 0C to +85C
+4.75V to +5.25V
-1.0V to +1.0V
-0.5V to +5.5V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
ECL VCC = +5.0V 5%, TTL VCC = +5.0V 5%, GND = 0V Symbol Parameter VIH Input HIGH Voltage Data OE VIL Input LOW Voltage Data OE VBB VOH VOL IIH Output Reference Voltage Output HIGH Voltage (TTL) Output LOW Voltage (TTL) Input HIGH Current Data OE IIL IBVI ICBO IOZH IOZL ICC ICCZ ICCL ICCH IOS VDiff VCM VCD Input LOW Current Input Breakdown Current Input Leakage Current 3-STATE Current Output HIGH 3-STATE Current Output LOW ECL Supply Current TTL Supply Current TTL Supply Current TTL Supply Current HIGH Output Short-Circuit Current Differential Input Voltage Common Mode Voltage Clamp Diode Voltage 13 10 8 0.4 -150 150 ECL VCC - 2.0 ECL VCC - 0.5 -1.2 OE OE -10 50 -50 30 20 17 2.0 -60 ECL VCC - 1.38 2.7 0.5 50 20 -200 10 Min Max Units V V V V V V V A A A A A A A mA mA mA mA mA mV V V IIN = -18 mA 3-STATE Low State HIGH State VOUT = 0.0V, VCC = +5.25 Required for Full Output Swing Conditions Guaranteed HIGH Signal for ALL Inputs (with One Input Tied to VBB) Guaranteed HIGH Signal (TTL) Guaranteed LOW Signal for ALL Inputs (with One Input Tied to VBB) Guaranteed LOW Signal (TTL) IBB = 0.0 mA or -1.0 mA IOH = -3 mA IOL = 24 mA VIN = VIH(Max), D0-D5 = VBB, D0-D5 = VIL(Min) VIN = 2.7V (TTL) VIN = 0.5V (TTL) VIN = 7.0V (TTL) VIN = GND, D0-D5 = VBB D0-D5 = VIL(Min) VOUT = +2.7V VOUT = +0.5V
ECL VCC - 1.165 ECL VCC - 0.870 2.0 ECL VCC - 1.830 ECL VCC - 1.475 0.8 ECL VCC - 1.26
3
www.fairchildsemi.com
100390
DIP AC Electrical Characteristics
VCC = 5.0V 5%; TC = 0C to +85C Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Parameter Min Maximum Clock Frequency Propagation Delay Data to Output Output Enable Time 100 3.5 2.7 2.4 2.9 2.3 7.2 4.8 4.0 5.8 3.9 TC = 0C Max TC = +25C Min 100 3.5 2.7 2.4 2.9 2.2 6.8 4.8 4.0 5.4 3.9 Max TC = +85C Min 100 3.5 3.0 2.6 2.7 2.2 6.7 5.1 4.2 5.1 3.9 Max MHz ns ns ns Figure 1 Figure 2 Figure 2 Units Figure Number
SOIC and PLCC Package AC Electrical Characteristics
VCC = 5.0V 5%; TC = 0C to +85C Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Parameter Maximum Clock Frequency Propagation Delay Data to Output Output Enable Time TC = 0C Min 100 3.5 2.7 2.4 2.9 2.3 7.0 4.6 3.8 5.6 3.7 Max TC = +25C Min 100 3.5 2.7 2.4 2.9 2.2 6.6 4.6 3.8 5.2 3.7 Max TC = +85C Min 100 3.5 3.0 2.6 2.7 2.2 6.5 4.9 4.0 4.9 3.7 Max Units MHz ns ns ns Figure 1 Figure 2 Figure 2 Figure Number
www.fairchildsemi.com
4
100390
Switching Waveforms
FIGURE 1. Data to Output Propagation Delay
FIGURE 2. Enable/Disable Propagation Delay
Test Circuit
Notes: GND = 0V, ECL VCC = +5V, TTL VCC = +5V L1 and L2 = equal length 50 impedance lines 50 terminators are internal to S/H measurement unit Decoupling 0.1 F from GND to ECL VCC and TTL V CC All unused outputs are loaded with 500 to GND CL = Fixture and stray capacitance = 50 pF Switch S1 is open for tPLH, tPHL, tPHZ and tPZH tests Switch S1 is closed only for tPLZ and tPZL tests
FIGURE 3. AC Test Circuit
5
www.fairchildsemi.com
100390
Application Notes
1. Device performance will be enhanced by the use of dual VCC power planes as illustrated in the Application Figures 4, 5. This will minimize the coupling of TTL switching noise into the primary reference to the ECL circuitry and take full advantage of the 100390's on chip VCC partitioning. 2. The device's partitioned VCC may be operated from two 5V, 5% tolerance, supplies provided that they are ramped up/down together so that the max differential is 1V. This is to prevent overstress to internal ESD diodes. If the ECL driver to the F390 is powered from a separate supply, it must obey this sequence rule also. 3. Glitch-free power up, independent of Data input levels, is achieved if TTL logic HIGH is held on the Output Enable pin during ramping up/down of the VCC supply. 4. Undefined output states can occur for some invalid combinations. See Truth Table. This should be avoided to prevent possible oscillation or increased power consumption due to TTL outputs biased into a quasi state with both pullup and pulldown stages partially on. 3-STATEing the outputs will counteract the effects of invalid input states. 5. Pins 8, 15, and 22 on the 28-pin PLCC package are tied to the chip's substrate and are named GNDs. These pins are electrically common to the ground pins 1, 2, and 28. For best thermal performance, tie the GND pins to the circuit ground plane. They may be tied to an electrically isolated thermal dissipation plane or may float. 6. Figure 4 illustrates typical differential input operation. 7. Figure 5 illustrates typical single-ended input operation.
FIGURE 4.
FIGURE 5.
www.fairchildsemi.com
6
100390
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E
7
www.fairchildsemi.com
100390 Low Power Single Supply Hex PECL-to-TTL Translator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

▲Up To Search▲

Price & Availability of 100390

	To Download 100390 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .